1. Technical Field
This invention relates to storage registers, and more particularly to a clocked register of the J-K flip/flop type.
2. Discussion
Storage registers are used in a wide variety of applications to transfer information at precise times to other components of digital and analog circuits. One common type of flip/flop in use is a J-K flip/flop. With the J-K flip/flop, information previously on its "SET" and "RESET" inputs is transferred to its outputs on the trailing edge of a clock pulse applied to a clock input of the flip/flop.
A problem can arise with such flip-flops if there is noise on the clock signal line. In such instances, the register may be fooled into believing that a trailing edge of a clock pulse has occurred when in fact only a noise spike has occurred on the clock pulse align. Accordingly, the register may erroneously respond before the trailing edge of a valid clock pulse is received.
Another problem with storage registers of the J-K flip/flop type is race conditions occurring between an input and an output register of the flip/flop. Such race conditions occur because there is no well-defined voltage range for the clock pulse signal during which both the input and output register of the flip/flop are inactive.
Accordingly, there is a need for a J-K flip/flop type register having input and output registers which are both inactive within a well-defined voltage range of the clock pulse, and which are therefore much less susceptible to spurious operation because of noise on the clock pulse line and race conditions developing between the two registers.
More particularly, there is a need for a J-K flip/flop having an input and an output register, where the input register is only responsive to a clock signal when the clock signal is below a predetermined value, is inactive when the clock signal is above the predetermined value, and where the output register is only responsive to the clock signal when the clock signal is above a second predetermined level. Such a circuit arrangement would provide a J-K flip/flop where the input and output registers are both inactive when the clock pulse signal is between the first and second predetermined levels. This would help insure that the input and output registers will ignore any noise present on the clock pulse line and therefore help to prevent race conditions from developing between the two registers.